1. Field of the Invention
The present invention relates to power semiconductor devices and, more particularly, to a MOS-controlled thyristor of a planar structure wherein p-channel and n-channel MOSFET's have a common gate and a main thyristor is operable by a static induction effect and a MOS-controlled thyristor of a vertical structure wherein vertical p-channel and n-channel MOSFET's have a common gate and a main thyristor is operable by a base resistance effect, JFET effect, or static induction effect.
2. Description of the Prior Art
FIG. 15 schematically illustrates the basic construction of a MOS controlled thyristor, which was proposed by Temple of General Electric Co. Reference numeral 1 denotes an anode electrode, 2 an anode region, 3 an n-type buffer layer, 5 a high resistivity layer, 6 a p-type base layer, 7 a first conductivity type layer, 8 a cathode region, 9 a cathode electrode, 10 a MOS gate electrode, and 11 a second conductivity type layer. The second conductivity type layer 11 and the p-type base layer 6 operate also as a main electrode region of a p-channel MOSFET, and a p-MOS channel is formed in the vicinity of the first conductivity type layer 7 as indicated by 7'. Similarly, the first conductivity type layer 7 and the high resistivity layer 5 operate also as a main electrode region of an n-channel MOSFET, and an n-MOS channel is formed in the vicinity of the p-type base layer as indicated by 6'. The MOS gate electrode 10 is common to both of the n-MOSFET and the p-MOSFET. The n.sup.+ -type cathode region, the p-type base layer 6, the n.sup.- -type high resistivity layer 5, the n.sup.+ -type buffer layer 3 and the p.sup.+ -type anode region 2 constitute a main thyristor, which is turned ON and OFF by the application of positive and negative pulse voltages. With the construction of FIG. 15, holes which are carriers stored in the p-type base layer 6 are not drawn out therefrom to an external gate as in a GTO but instead they are short-circuited via the p-channel MOSFET to the second conductivity type layer 11 short-circuited to the cathode electrode 9. What is called a shorted cathode structure is implemented by the p-channel MOSFET between the p-type base layer 6 and the cathode region 8. On the other hand, the n-channel MOSFET functions to turn ON the main thyristor by injecting electrons from the cathode region 8 and the first conductivity type layer 7 into the n.sup.- -type high resistivity layer 5 which serves as a second base layer, through the channel of the n-MOSFET.
FIG. 16 schematically illustrates, in section, the construction of another conventional MOS-controlled thyristor, which was published by a research group of Asea Brown Boveri Inc. This construction is disclosed in F. Bauer et al., "Current-Handling and Switching Performance of MOS-controlled Thyristor (MCT) Structures," IEEE EDL Vol. 12, No. 6, June 1991, for instance. In FIG. 16 the parts corresponding to those in FIG. 15 are identified by the same reference numerals. The illustrated structure differs from FIG. 15 example in that the n-MOSFET is not provided for each channel and in that the n-type buffer layer 3 in FIG. 15 is not provided. This prior art example has its feature in that the p-channel MOSFET for cathode short-circuit use is provided around the cathode region 8 in the wide p-type base layer 6. The FIG. 16 example facilitates the formation of a multichannel structure as compared with the FIG. 15 example but calls for the formation of another n-channel MOSFET for turning ON the main thyristor. FIG. 17 is a sectional view schematically illustrating the structure disclosed in C. Ronsisvalle et al., "HIGH POWER MOS-CONTROLLED-THYRISTOR USING THE PARALLEL CONTACTING TECHNOLOGY FOR DEVICES ON THE SAME WAFER," EPE FIRENZE, 1991, pp. 267-269. The parts corresponding to those in FIGS. 15 and 16 are identified by the same reference numerals. This example has its structural feature in that an n.sup.+ -type region 16 is provided around the p-type base layer 6 to form an n-channel MOSFET in the surface region on the layer 6 at one end thereof.
In the conventional MOS-controlled thyristors of FIGS. 15 through 17, the main thyristor has the same structure as a conventional four-layered thyristor or SCR. In Japanese Patent Laid-Open Gazette No. 278119/89 (filed Apr. 30, 1988) there is described a driving method for a MOS-controlled thyristor wherein the main thyristor is formed as a static induction thyristor and a MOS-controlled system is used, and furthermore, it is stated in the gazette that the thyristor is called a MOS-controlled static induction thyristor in the case where its peripheral elements are integrated. The MOS-controlled static induction (SI) thyristor has a high gate current amplification factor, and hence is operable on a small gate signal. In Nishizawa, "SI Thyristors Hold Promise for Improved DC Power Transmission," PCI & Motor 'Con 88, Munich, West Germany 1988, June 6-8, or Nishizawa and Tamamushi, "Recent Development and Future Potential of the Power Static Induction (SI) Devices," Proceedings of the Third International Conference on Power Electronics and Variable-Speed Drives, Vol. 291, pp. 21-24, July 1988 it is described that the MOS-controlled SI thyristor with only a gate capacitor integrated was made by way of trial up to 600V-3A class and operable with only a gate capacitor C.sub.G.
Moreover, an example of a MOS-controlled SI thyristor of the type that only the gate capacitor C.sub.G and/or p-channel MOS transistor for turn OFF use are integrated is disclosed in Japanese Patent Laid-Open Gazette No. 292770/91 or 292769/91.
It is difficult, however, to sufficiently drive a large-capacity SI thyristor by a gate signal of a transient differential waveform which is applied via the gate capacitor. To turn ON the large-capacity SI thyristor uniformly throughout it, it is necessary that the gate capacitor C.sub.G be provided by forming a gate oxide layer on the gate over the entire area of the wafer surface. The capacitance of the gate capacitor C.sub.G depends virtually on the thickness of the gate oxide layer, but it is hard to form such a thin oxide layer on the gate over the entire area of the wafer surface. It is preferable that the gate capacitor C.sub.G be large in capacitance, since the gate drive signal applied across the gate and cathode, but it is difficult to form the gate capacitor C.sub.G large as compared with the gate-cathode capacitance C.sub.GK. As mentioned above, it has been ascertained that MOS-controlled SI thyristors up to 600V-3A class are operable with only the gate capacitor when it has a small capacitance.
It is therefore desirable to implement a planar MOS-controlled thyristor structure which ensures stable ON-OFF control of a large-capacity thyristor and is easy to manufacture. It is also desirable that the MOS-controlled thyristor be superior to the conventional thyristor in the ratio di/dt for the turn-ON operation, and hence afford reduction of the turn-ON time t.sub.gt.
On the other hand, an insulated gate bipolar transistor (IGBT), which is inferior to the MOS-controlled thyristor in terms of current capacity but operates similarly under insulated gate control, is superior to the MOS-controlled thyristor in terms of integration density. FIG. 18 is a sectional view schematically illustrating the IGBT structure. Reference numeral 1' indicates a p-type emitter electrode, 8' a p-type collector layer, 9' an IGBT collector electrode, 11' an IGBT emitter electrode, and 17 an IBGT p-type base layer. The other regions 3, 5, 10, 14 and 15 are the same as those in FIG. 17. In FIGS. 15 and 18, reference character L indicates the substantial width of a unit cell. It will be seen that the cell width L of the MOS-controlled thyristor (FIG. 15) is larger than the cell width L of the IGBT (FIG. 18) by the width of a diffused region of the p-type base layer 6. It is considered that the value L is a dimension necessary to implement the unit cell. Assuming that sizing rules for their microfabrication are the same, the value L in FIG. 15 is about 7/5=1.4 times as large as the value L in FIG. 18. To improve the turn-ON characteristic of the MOS-controlled thyristor and reduce its ON-voltage, it is desirable to reduce the unit cell width L and hence increase the integration density.